1. Field of the Invention
The present invention relates to a PLL (phase locked, loope) for direct modulation suitable for use, for example; in the transmitter for radio telephony.
2. Description of the Prior Art
In transmitters for use in mobile communication, frequency synthesizers employing a PLL are frequently used in the circuits for generating the carrier wave. In the modulation, although systems to frequency modulate an output signal of a reference frequency signal generator formed of the PLL have been generally used, currently direct modulation systems are used, in which the PLL is subjected to a frequency modulation. This is because the direct modulation system can be designed easily and cost reduction can thereby be achieved.
FIG. 5 is a block diagram showing a frequency synthesizer of the described type. Referring to the figure, reference numeral 1 denotes a PLL IC (for example, FUJITSU make MB87001A) composed of a programmable frequency divider, a phase comparator, and others. The PLL IC 1 is adapted such that its programmable frequency divider is supplied with data for establishing the frequency dividing ratio. The inputs of its phase comparator are supplied with an output signal (frequency f.sub.p) of the above described programmable frequency divider and an oscillating output (reference frequency f.sub.r) of an oscillator 2. The PLL IC is adapted to achieve three conditions: first, it brings its output Tank to high impedance and its output Sink to an "L" level when f.sub.p =f.sub.r ; second, it brings both its outputs Tank and Sink to an "L" level when f.sub.r &gt;f.sub.p ; third, it brings its output Tank to high impedance and its output Sink to an "H" level when f.sub.r &lt;f.sub.p. Reference numeral 3 denotes a charge pump amplifier portion, which is a circuit to shorten the charging and discharging times of capacitors within a low pass filter 4 to thereby shorten the lock-in time of the PLL. The charge pump amplifier 3 is composed of transistors Q1 and Q2, their emitter resistors R1 and R2, and resistors R3 and R4 inserted between the base and emitter of each thereof. The bases of the transistors Q1 and Q2 are connected with the outputs Tank and Sink through resistors R5 and R6, respectively, and the common collector of the transistors Q1 and Q2 is connected with the input of the low pass filter 4. The low pass filter 4 is composed of resistors R7 and R8 inserted in series between its input and output, a capacitor C2 inserted between its output and ground, and a resistor R9 and a capacitor C1 inserted in series between the junction of the resistors R7 and R8 and ground. Reference numeral 5 denotes a voltage controlled oscillator receiving an output voltage of the low pass filter 4 at its frequency controlling terminal. The voltage controlled oscillator 5 is adapted such that its output signal is modulated by a signal MOD. The output signal of the voltage controlled oscillator 5 is divided in frequency by a prescaler 6 and is supplied to the input of the programmable frequency divider circuit of the PLL IC 1.
The circuit shown in FIG. 5 is adapted such that, when f.sub.r &gt;f.sub.p, both the outputs Tank and Sink of the PLL IC 1 go to an "L" level. The transisitor Q1 is turned ON and the transistor Q2 is turned OFF so that the capacitors C1 and C2 are charged. As a result, the output voltage of the low pass filter 4 is raised, the output frequency of the voltage controlled oscillator 5 is increased, and thus, the frequency f.sub.p increases to come close to f.sub.r. When f.sub.r &lt;f.sub.p, the output Tank obtains high impedance and the output terminal Sink goes to an "H" level. The transistor Q1 is turned OFF, the transistor Q2 is turned ON, and the capacitors C1 and C2 are discharged. As a result, the output voltage of the low pass filter 4 is lowered, the output frequency of the voltage controlled oscillator 5 is decreased, and thus, the frequency f.sub.p comes close to f.sub.r. When f.sub.p =f.sub.r, the output Tank of the PLL IC 1 obtains high impedance, the output Sink goes to an "L" level, and hence both the transistors Q1 and Q2 are turned OFF. As a result, the capacitors C1 and C2 are neither charged nor discharged and the output voltage of the low pass filter 4 remains uncharged. Thus, the output frequency of the voltage controlled oscillator 5 remains unchanged and the condition f.sub.p =f.sub.r is maintained.
In the described manner, within the response range of the PLL, the circuit always functions such that the condition f.sub.p =f.sub.r is attained.
As understood from the foregoing description, the circuit always functions such that the condition f.sub.p =f.sub.r is attained within the response range of the PLL, and hence, the region of frequencies of the signal MOD at which modification is possible exists on the outside of the response range. As a consequence, a phase error response characteristic, as shown in FIG. 6 indicates the condition for modulation. The frequency f.sub.0, shown in FIG. 6, represents the self-resonant frequency of the PLL (generally, 300-600 Hz). As apparent from FIG. 6, the frequency region in which good modulation is achieved is the region higher than the self-resonant frequency f.sub.0 (the region indicated by the arrow). In the region lower than the self-resonant frequency the PLL tracks and suppresses the frequency variations produced by the frequency modulation to thereby suppress the frequency variations making good modulation unattainable. In this case, the self-resonant frequency f.sub.0 is 300-600 Hz, while the frequency range of the signal MOD, when a voice signal for radio telephony or the like is treated, is in the so-called audio range from 300 Hz to 3 kHz. Accordingly, a flat modulating characteristic is not obtained at the lower frequencies of the signal MOD, so that voice signals, of the like, are not accurately transmitted. The ideal characteristic of the phase comparator within a PLL IC is such as shown by a solid line in FIG. 7. In actuality, the characteristic as indicated by dotted lines in FIG. 7 is obtained instead because of irregularity in the manufacture of semiconductors. Thus, a dead zone is produced around the frequency f.sub.0 to be locked in. As a result, there has been a difficulty that no response is obtained to disturbances having a low frequency component such as the ripple of the power supply. Recently, a special design as created which elminates the dead zone and improves the response to external disturbing noises. This is shown in FIG. 8. However, when the dead zone of the phase comparator is eliminated, the self-resonant frequency f.sub.0 of the PLL increases. As a result, the modulating characteristic in the audio frequency range becomes worse than before in the higher frequency region.